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A Method of Test Generation for Iterative Logic Arrays (特集:VLSIプロセッサ及び新アーキテクチャLSI技術,一般)

Paper Details
Authors:
Kwame Osei Boateng
寛 高橋
雄三 高松
Publication Date: 1999-04-16
VLSI and Analog Circuit TestingComputer ScienceHardware and ArchitecturePhysical Sciences
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